EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 172

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 71. Example: Multi-PWM Addressing
PS019209-0504
Parameter
Timer Reload Value
PWM0 rising edge
PWM0 falling edge
PWM1 rising edge
PWM1 falling edge
PWM enable
PWM0 enable
PWM1 enable
Multi-PWM enable
Prescaler Divider = 4
PWM nonoverlapping delay = 0
PWM Master Mode
Modification of Edge Transition Values
In PWM Master mode, the pair of output signals generated from the PWM0 gener-
ator (PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting
TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master mode. Assuming the out-
puts are all enabled and no AND/OR gating is used, all four PWM output pairs
transition simultaneously under the direction of PWM0 and PWM0. In PWM Mas-
ter mode, the outputs can still be gated individually using the AND/OR gating func-
tions described in the next section. Multi-PWM mode and the individual PWM
outputs must be enabled along with PWM Master mode. It is possible to enable or
disable any combination of the 4 PWM outputs while running in PWM Master
mode.
Special circuitry is included for the update of the PWM edge transition values.
Normal use requires that these values be updated while the PWM generator is
running.
Control Register(s)
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H,
TMR3_PWM0R_L}
{TMR3_PWM0F_H,
TMR3_PWM0F_L}
{TMR3_PWM1R_H,
TMR3_PWM1R_L}
{TMR3_PWM1F_H,
TMR3_PWM1F_L}
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[PWM1_EN]
TMR3_PWM_CTL1[MPWM_EN]
TMR3_CTL[CLK_DIV]
TMR3_PWM_CTL2[PWM_DLY]
P R E L I M I N A R Y
Programmable Reload Timers
Product Specification
Value
000Ch
0008h
0004h
0006h
0007h
1
1
1
1
00b
0000b
eZ80F91 MCU
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