EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 307
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 307 of 396
- Download datasheet (5Mb)
PS019209-0504
ZDI Clock and Data Conventions
ZDI START Condition
The two pins used for communication with the ZDI block are the ZDI clock pin
(ZCL) and the ZDI data pin (ZDA). On the eZ80F91, the ZCL pin is shared with
the TCK pin while the ZDA pin is shared with the TDI pin. The ZCL and ZDA pin
functions are only available when the On-Chip Instrumentation is disabled and the
ZDI is therefore enabled. For general data communication, the data value on the
ZDA pin can change only when ZCL is Low (0). The only exception is the ZDI
START bit, which is indicated by a High-to-Low transition (falling edge) on the
ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the most-significant bit (bit 7) of each byte
being first in time, and the least-significant bit (bit 0) last in time. All information is
passed between the master and the slave in 8-bit (single-byte) units. Each byte is
transferred with nine clock cycles: eight to shift the data, and the ninth for internal
operations.
All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low
transition of ZDA when ZCL is High. The ZDI slave on the eZ80F91 device contin-
ually monitors the ZDA and ZCL lines for the START signal and does not respond
to any command until this condition is met. The master pulls ZDA Low, with ZCL
High, to indicate the beginning of a data transfer with the ZDI block. Figures 53
and 54 illustrate a valid ZDI START signal prior to writing and reading data,
respectively. A Low-to-High transition of ZDA while the ZCL is High produces no
effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as
illustrated in Figure 53. Data is shifted out during a Read from the ZDI block on
the falling edge of ZCL as illustrated in Figure 54. When an operation is com-
pleted, the master stops during the ninth cycle and holds the ZCL signal High.
P R E L I M I N A R Y
Product Specification
ZiLOG Debug Interface
eZ80F91 MCU
288
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