EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 251

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
Software Reset.
Reset Register (
the
I
The I2C_SAR register provides the 7-bit address of the I
and allows 10-bit addressing in conjunction with the
I2C_SAR[7:1] = SLA[6:0] is the 7-bit address of the I
mode. When the I
SLAVE mode. I2C_SAR[7] corresponds to the first bit received from the I
When the register receives an address starting with
11110b), the I
The I
generate an interrupt at this point). After the next byte of the address (I2C_XSAR)
is received, the I
I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The
full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 124.
Table 124. I
(I2C_SAR = 00C8h)
I
The I2C_XSAR register is used in conjunction with the I2C_SAR register to pro-
vide 10-bit addressing of the I
forms the lower 8 bits of the 10-bit slave address. The full 10-bit address is sup-
plied by {I2C_SAR[2:1], I2C_XSAR[7:0]}.
When the register receives an address starting with
11110b), the I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
2
2
C Slave Address Register
C Extended Slave Address Register
I2C_CTL
2
C sends an ACK after receiving the I2C_SAR byte (the device does not
2
C Slave Address Register
register to 0 and sets the I
2
2
C recognizes that a 10-bit slave addressing mode is being selected.
C recognizes that a 10-bit slave addressing mode is being selected.
I2C_SRR
Perform a software reset by writing any value to the I
2
C generates an interrupt and enters SLAVE mode.Then
Value Description
00h–
7Fh
0
1
2
C receives this address after a START condition, it enters
R/W
7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address
when operating in 10-bit mode.
I
I
P R E L I M I N A R Y
). A software reset clears the STP, STA, and IFLG bits of
7
0
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
2
C when in SLAVE mode. The I2C_SAR value
R/W
6
0
R/W
2
C back to an idle state.
5
0
R/W
4
0
F7h
F7h
I2C_XSAR
2
C when in 7-bit SLAVE
R/W
3
0
2
to
to
C when in SLAVE mode
Product Specification
F0h
F0h
R/W
2
0
I
register.
(I2C_SAR[7:3] =
(I2C_SAR[7:3] =
2
C Serial I/O Interface
eZ80F91 MCU
R/W
2
C Software
1
0
2
C bus.
R/W
0
0
232

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