EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 133

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
Flash Frequency Divider Register
The 8-bit frequency divider allows the programming of Flash memory over a
range of system clock frequencies. Flash can be programmed with system clock
frequencies ranging from 154 kHz to 50 MHz. The Flash controller requires an
input clock with a period that falls within the range of 5.1 6.5 µs. The period of the
Flash controller clock is set in the Flash Frequency Divider Register. Writes to this
register are allowed only after it is unlocked via the FLASH_KEY register. The
Flash Frequency Divider Register value required vs. the system clock frequency
is shown in Table 38. System clock frequencies outside of the ranges shown are
not supported. Register values for the Flash Frequency Divider are shown in
Table 39.
Table 38. Flash Frequency Divider Values
Table 39. Flash Frequency Divider Register
(FLASH_FDIV = 00F9h)
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
Bit
Position
[7:0]
FLASH_FDIV
System Clock Frequency
CEILING(3.01) is 4.
616 kHz–50 MHz
154–196 kHz
308–392 kHz
462–588 kHz
Value Description
01h–
FFh
R/W*
Divider value for generating the required 5.1-6.5 µs Flash
controller clock period.
P R E L I M I N A R Y
7
0
R/W*
CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
6
0
R/W*
5
0
Flash Frequency Divider Value
R/W*
4
0
R/W*
1
2
3
3
0
Product Specification
R/W*
2
0
eZ80F91 MCU
R/W*
1
0
Flash Memory
R/W
0
1
114

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