EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 98

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 18. Z80 Bus Mode Read States
Table 19. Z80 Bus Mode Write States
PS019209-0504
STATE T1
STATE T2
STATE T3
STATE T1
STATE T2
STATE T3
eZ80 Bus Mode
Z80 Bus Mode
The Read cycle begins in State T1. The
and the associated Chip Select signal is asserted.
During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional wait states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80F91 at the
rising edge of the CPU system clock at the end of State T3.
The Write cycle begins in State T1. The
and the associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional wait states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered.
Control Registers. The number of CPU system clock cycles per bus mode state is
also independently programmable. For Intel bus mode, multiplexed address and
data can be selected, in which the lower byte of the address and the data byte
both use the data bus, DATA[7:0]. Each of the bus modes is explained in more
detail in the following sections.
Chip selects configured for eZ80 bus mode do not modify the bus signals from the
CPU. The timing diagrams for external Memory and I/O Read and Write opera-
tions are shown in the
for each chip select is eZ80 mode.
Chip selects configured for Z80 mode modify the eZ80
Z80 microprocessor address and data bus interface signal format and timing. Dur-
ing Read operations, the Z80 Bus mode employs three states—T1, T2, and T3—
as described in Table 18.
During Write operations, Z80 Bus mode employs 3 states—T1, T2, and T3—as
described in Table 19.
AC Characteristics
P R E L I M I N A R Y
CPU
CPU
drives the address onto the address bus,
drives the address onto the address bus
section on page 348. The default mode
®
bus signals to match the
Chip Selects and Wait States
Product Specification
WAIT
WAIT
eZ80F91 MCU
) are asserted
) are asserted
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