EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 32
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 32 of 396
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Table 2. Pin Identification on the eZ80F91 Device (Continued)
PS019209-0504
LQFP
Pin #
43
44
45
46
47
48
49
Note: *PHY represents the physical layer of the OSI model.
BGA
Pin#
L3
H5
L4
M4
K4
G6
M5
Symbol
DATA4
DATA5
DATA6
DATA7
V
V
IORQ
DD
SS
Function
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Input/Output
Request
P R E L I M I N A R Y
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional, Active
Low
Description
The data bus transfers data to
and from I/O and memory
devices. The eZ80F91 drives
these lines only during Write
cycles when the eZ80F91 is the
bus master.
The data bus transfers data to
and from I/O and memory
devices. The eZ80F91 drives
these lines only during Write
cycles when the eZ80F91 is the
bus master.
The data bus transfers data to
and from I/O and memory
devices. The eZ80F91 drives
these lines only during Write
cycles when the eZ80F91 is the
bus master.
The data bus transfers data to
and from I/O and memory
devices. The eZ80F91 drives
these lines only during Write
cycles when the eZ80F91 is the
bus master.
Power Supply.
Ground.
IORQ indicates that the CPU is
accessing a location in I/O space.
RD and WR indicate the type of
access. The eZ80F91 device
does not drive this line during
RESET. It is an input in bus
acknowledge cycles.
Product Specification
Architectural Overview
eZ80F91 MCU
13
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