EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 87

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 12. Vectored Interrupt Operation (Continued)
PS019209-0504
Memory
Mode
Z80 Mode
ADL Mode
ADL
Bit
0
1
Interrupt Priority Registers
The eZ80F91 provides two interrupt priority levels for the maskable interrupts.
The default priority (or Level 0) is indicated in
maskable interrupt can increase to Level 1 (a higher priority than any Level 0
interrupt) by setting the appropriate bit in the Interrupt Priority Registers, which
are shown in Table 13.
MADL
Bit
1
1
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT[8:0], bus by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [8:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the SPL stack.
Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode
(because ADL = 0).
Set the ADL mode bit to 1.
The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
PC[23:0]
The interrupt service routine must end with RETI.L
IEF1
IEF2
The Starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
The ADL mode bit remains set to 1.
The interrupt vector address is located at {I[15:1], IVECT[8:0]}.
PC[23:0]
The interrupt service routine must end with RETI.L
0
0
0
0
( { I[15:1], IVECT[8:0] } ).
( { I[15:1], IVECT[8:0] } ).
P R E L I M I N A R Y
Table
11. The default priority of any
Product Specification
Interrupt Controller
eZ80F91 MCU
68