EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 154

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Timer Port Pin Allocation
The initial value for the OCx pins in OUTPUT COMPARE mode is 0 by default. It
is possible to initialize this value to 1, or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state
provided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare
events, the pin stays at the forced value until OCx_MODE is changed. After
release, it retains the forced value until modified by an OUTPUT COMPARE
event.
Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUT-
PUT COMPARE events, and sets output 0 as the master. As a result, outputs 1, 2,
and 3 are caused to disregard output-specific configuration and comparison val-
ues and instead mimic the current settings for output 0.
The OCx bits in the TMR3_IIR register are set whenever the corresponding timer
compares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to gener-
ate a timer interrupt.
The eZ80F91 device timers interface to the outside world via Ports A and B.
These ports are also used for general purpose I/O as well as other assorted func-
tions. Table 53 lists the timer pins and their respective functions.
Table 53. GPIO Mode Selection When Using Timer Pins
Port
A
GPIO Port
Bits
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
GPIO Port
P R E L I M I N A R Y
Mode
7
7
7
7
7
7
7
7
MPWM_EN = 0
PAIR_EN = 0
PWM_CTL1
PWM_CTL1
TOUT0
TOUT1
OC0
OC1
OC2
OC3
EC1
Timer Function
Programmable Reload Timers
MPWM_EN = 1
PAIR_EN = 1
Product Specification
PWM_CTL1
PWM_CTL1
PWM0
PWM1
PWM2
PWM3
PWM0
PWM1
PWM2
PWM3
eZ80F91 MCU
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