EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 238

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

I
PS019209-0504
2
C Serial I/O Interface
I
2
C General Characteristics
The Inter-Integrated Circuit (I
face that can operate in four modes:
•
•
•
•
The I
SCL and SDA are bidirectional lines connected to a positive supply voltage via an
external pull-up resistor. When the bus is free, both lines are High. The output
stages of devices connected to the bus must be configured as open-drain outputs.
Data on the I
mode, or up to 400 kbps in FAST mode. One clock pulse is generated for each
data bit transferred.
Clocking Overview
If another device on the I
mode, the I
clock is determined by the device that generates the shortest High clock period.
The Low period of the clock is determined by the device that generates the long-
est Low clock period.
A slave can stretch the Low period of the clock to slow down the bus master. The
Low period can also be stretched for handshaking purposes. This result can be
accomplished after each bit transfer or each byte transfer. The I
clock after each byte transfer until the IFLG bit in the I2C_CTL register is cleared
to 0.
Bus Arbitration Overview
In MASTER mode, the I
I
nal Low, arbitration is lost. If arbitration is lost during the transmission of a data
byte or a Not Acknowledge (NACK) bit, the I
tion is lost during the transmission of an address, the I
mode so that it can recognize its own slave address or the general call address.
2
C bus as a logic 1. If another device on the bus overrules and pulls the SDA sig-
MASTER TRANSMIT
MASTER RECEIVE
SLAVE TRANSMIT
SLAVE RECEIVE
2
C interface consists of a Serial Clock (SCL) and Serial Data (SDA). Both
2
C synchronizes its clock to the I
2
C bus can be transferred at a rate of up to 100 kbps in STANDARD
2
C checks that each transmitted logic 1 appears on the
2
P R E L I M I N A R Y
C bus drives the clock line when the I
2
C) serial I/O bus is a two-wire communication inter-
2
2
C bus clock. The High period of the
C returns to an idle state. If arbitra-
2
C switches to SLAVE
Product Specification
I
2
2
2
C is in MASTER
C Serial I/O Interface
C stretches the
eZ80F91 MCU
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