EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 336

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
Table 204. Pin to Boundary Scan Cell Mapping (Continued)
PS019209-0504
Pin
A13
A12
A12
A11
A11
A10
A10
A9
A9
A8
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
3. MREQ,
shown to be associated with the least-significant bit that they control.
with D[0].
IORQ
, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
OEN
Input
Input
Input
Input
Input
Input
Input
Scan Cell #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
P R E L I M I N A R Y
Pin
PC6
PC6
PC6
PC5
PC5
PC5
PC4
PC4
PC4
PC3
PC3
PC3
PC2
PC2
PC2
PC1
PC1
PC1
PC0
PC0
PC0
PD7
PD7
PD7
PD6
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Product Specification
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
On-Chip Instrumentation
eZ80F91 MCU
Scan Cell #
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
317

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