PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 100

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 4-4
Data-Rate
Mode
2 x 6/12/32
time slots/frame
1 x 64
time slots/frame
Preliminary Data Sheet
Table 4-3
Data Rate
2 x 2.048 Mbit/s
2 x 384 kbit/s
2 x 768 kbit/s
1 x 4.096 Mbit/s
Note: In 2 x 384 / 768 kbit/s mode, only the first 6 / 12 bytes of each block are used.
4.3.2.3
The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer
space is directed automatically to the appropriate sub-buffer.
.
4.3.2.4
The IOMU may support different serial data rates of the IOM-2 interface:
• 384 kbit/s (6 time slots per frame)
• 768 kbit/s (12 time slots per frame)
• 2.048 Mbit/s (32 time slots per frame = 8 IOM-2 channels per frame)
• 4.096 Mbit/s (64 time slots per frame = 16 IOM-2 channels per frame)
The IOMU circular buffer may handle up to 64 time slots per frame. Thus, when in 4.096
Mbit/s mode, only IOM-2 port 0 is used. In this case IOM-2 port 1 remains in IDLE mode,
i.e. the DD1 output pin is tri-stated.
Note that when using any of the two lower data rates, both IOM-2 ports are used.
In all data rate modes, single rate Data Clock (DCL) or double rate Data Clock may be
selected.
DSP Access to the D-Buffer
IOM-2 Interface Data Rate Modes
D-Buffer Address Space
I-Buffer Logical Memory Mapping
in0
8000
801F
8000
803F
00
00
H
H
H
H
H
H
in0
- 1F
- 3F
-
-
Input Blocks
H
H
in1
8020
803F
-
20
H
H
H
4-16
in1
--
-
- 3F
H
D-Buffer
out0
8040
805F
8040
807F
40
40
H
H
H
H
out0
H
H
-
-
- 5F
- 7F
Output Blocks
Functional Description
H
H
out1
8060
807F
-
60
H
H
out1
H
-
--
- 7F
DELIC
2003-08
H