PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 223

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 9-9
Note: IREQ is deactivated due to P write operation to OBUSY register. In Motorola
9.4
The exact behavior required from the µP interface signals during a DMA access depends
on the following modes:
• Motorola or Intel Mode: Determined by the MODE input pin.
• Normal or ’fly-by’ Mode: Programmable in the control register of the µP interface.
In any mode, the DACK input is used to indicate that this is a DMA transaction, and to
select the DMA Mailbox. An activation via the CS signal is not required in such cases.
9.4.1
In this mode DS is used for timing the access, while R/W is used to distinguish between
DMA read transactions and DMA write transactions. The R/W input signal is used
differently in normal mode and in fly-by mode. The next table shows how R/W should be
used in each mode during DMA transactions:
Table 9-8
Mode
Normal (Non-Fly-By)
Fly-By
Preliminary Data Sheet
DSxCS
WR
IREQ
mode DS and CS together time the write access. In Intel mode WR alone times
the write access. For more details regarding the timing required during write
access to the DELIC, refer to section 9.2. The other signals required for a write
operation to OBUSY in each mode, are assumed to be driven.
DMA Access Timing
DMA Access Timing In Motorola Mode
IREQ Deactivation Timing
R/W Behavior During DMA Transactions in Normal and Fly-By Mode
R/W = ‘0’
Write DMA transaction.
(A response to DMA
transmitter request)
Read DMA transaction.
(A response to DMA
receiver request)
9-9
R/W = ‘1’
Read DMA transaction.
(A response to DMA receiver
request)
Write DMA transaction.
(A response to DMA transmitter
request)
t
DWI
Timing Diagrams
DELIC
2003-08