PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 154

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

RD_n
Note: Unused bits (x) read as ‘0’. The registers are reset upon every 8 kHz frame sync
6.2.1.4
The VIPSTR0-2 registers contain the status bits received from the dedicated VIP for
VIPs 0, 1, 2 respectively (all three registers have the same structure).
VIPSTR Register
Reset value: 0000
Preliminary Data Sheet
to avoid multiple data transmit/receive to/from the VIP.
15
7
x
VIP Status Registers
0 =
1 =
0 =
1 =
Read Request to VIP Status Register S_n (S/T, U
H
14
6
x
Normal operation
The clock recovering PLLs of all VIP channels operate on
positive line pulses only
No register read
The DSP reads the VIP register (during initialization,
debugging or error conditions). The register value is available
for the read operation in the consecutive frame (after the next
FSC).
Note: To avoid blocking, the DSP must not issue this bit during
read
13
x
5
normal operation.
12
DELAY(7:0)
x
4
6-14
11
3
x
Address:
10
2
x
Register Description
VIPSTR0: D0AC
VIPSTR1: D0AD
VIPSTR2: D0AE
PN
)
9
1
x
DELIC
2003-08
8
x
0
H
H
H
,
,