PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 153

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

EXREF
DELCH(2:0)
DELRE
SH_FSC
PLLPPS
Preliminary Data Sheet
The reference clock signal for the DELIC oscillator is generated from
the internal VIP_n Channel_m coded in these 3 bits and passed on via
pin REFCLK to the next cascaded VIP or directly to the DELIC
000 =
001 =
...
007 =
External Reference Clock Selection (LT-T)
0 =
1 =
Delay Measurement Channel Selection (U
Selects one of the eight Upn line interface channels of each VIP where
the delay is to be measured.
000 =
001 =
...
111 =
Delay Counter Resolution (U
Resolution of the delay counter.
0 =
1 =
Short FSC Pulse
0 =
1 =
PLL Positive Pulse Sensing
Reference clock provided by Channel_0
Reference clock provided by Channel_1
Reference clock provided by Channel_7
No external reference clock source. Reference clock is
generated
REFCLK(2:0) and passed on via REFCLK pin to VIP_n-1 or
directly to DELIC.
Reference clock is generated from external source via pin
INCLK and passed on via REFCLK pin to VIP_n-1 or directly to
DELIC. The internal reference clock generation logic is
disabled.
Note that VIP_0 has the highest priority in terms of clock
selection
Delay is measured in Upn Channel_0
Delay is measured in Upn Channel_1
Delay is measured in Upn Channel_7
Resolution of 65 ns (15.36 MHz period)
Resolution of 130 ns (7.68 MHz period)
Note: Using a resolution of 65 ns, the maximum delay of
The next FSC frame is no superframe
The next FSC is assumed as superframe
20.8 µs is not covered (refer to DELAY(7:0) bits)
from
6-13
internal
PN
)
VIP_n
PN
)
channel
Register Description
specified
DELIC
2003-08
in