PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 226

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 9-11 DMA Read-Transaction Timing in Motorola Mode
Note: R/W is shown for normal mode. In Fly-by mode, R/W should be low during DMA
9.4.2
In this mode, R and W are used for timing the access and to determine whether a DMA
read cycle or DMA write cycle has occured. R and W input signals are used in opposite
ways in normal mode and in fly-by mode.
The next table shows how R and W should be used in each mode during DMA
transactions:
Preliminary Data Sheet
DS
DACK
R/W
D
DREQR
read transactions.
DMA Access Timing in Intel/Infineon Mode
t
t
SRWS
SAS
t
WS
9-12
t
t
HSA
t
WS
HSRW
t
last byte
t
DSDV
DSR
Timing Diagrams
t
DSDT
DELIC
2003-08