PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 221

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 9-6
Parameter
ALE low before RD X CS falling edge t
ALE hold time after RD X CS rising
edge
ALE pulse width
A-bus setup time before ALE falling
edge
A-bus hold time after ALE falling edge t
RD X CS falling edge to D-bus valid
D-bus float after RD X CS rising edge t
Figure 9-6
9.3
The IREQ (Interrupt REQuest) output signal of the DELIC is activated upon a DSP write
operation to the OCMD register (OAK Mailbox command register). This operation sets
the OAK Mailbox busy bit (OBUSY), which drives directly the IREQ output signal. The
IREQ signal may be masked, by programming the MASK bit within the µP interface
Control Register (UPCR).
The microprocessor may force the DELIC to drive the interrupt vector over the data bus
by activation of the interrupt acknowledge input signal (IACK).
Preliminary Data Sheet
RDxCS
ALE
AD
Interrupt Acknowledge Cycle Timing
Timing For Read Cycle In Intel/Infineon Multiplexed Mode
Read Cycle in Intel/Infineon Multiplexed Mode
t
WL
t
Address
SAL
t
HRL
Symbol
t
t
t
t
HRL
HLR
WL
SAL
HAL
DRD
DRDH
t
HAL
9-7
min.
5
5
10
12
5
0
0
Limit Values
t
DRD
Data
max.
20
15
Unit
ns
ns
ns
ns
ns
ns
ns
t
DRDH
Timing Diagrams
t
HLR
Test
Condition
Output load
capacity of
50 pF
DELIC
2003-08