PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 96

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
During initialization the DSP writes a value with '0' in its LSB (other bits are of no
importance) to every History RAM address associated to an U
be scrambled, and a value with '1' in its LSB for every U
scrambled. The same values must be written to the descrambler history RAM.
The HRAM addresses are:
• 0x9000 - 0x9017 (scrambler U
• 0x9020 - 0x9037 (descrambler U
For example, in order to activate scrambling and descrambling for channel number 3, the
DSP must execute two write operations as follows:
• Write "xxxxxxxxxxxxxxx1" to address 0x9002
• Write "xxxxxxxxxxxxxxx1" to address 0x9022
These writes are executed only when the scrambler is in idle mode, i.e. value 0x0003
was written by the OAK to address 0xD010.
4.2.7.3
Data is received/transmitted at a nominal rate of 192 kbit/s. Each S/T data bit is
translated into two bits on IOM_2000: data (bit0) and control (bit1).
LT-S Mode Transmit Data Format
LT-S Mode Receive Data Format
7
D-channel
7
D-channel
S/T Mode
6
6
Operation Mode Command/Status bits
Operation Mode Command/Status bits
F
5
5
x
a
PN
B1 - channel data
B2 - channel data
B1-channel data
B2-channel data
PN
channel 0..23)
F
channel 0..23)
4
4
x
a
4-12
M
3
3
x
S
2
2
x
PN
Functional Description
PN
channel that must be
channel that is not to
1
x
1
x
0
x
0
x
DELIC
2003-08