PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 121

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 4-14 GHDLC Receive and Transmit Buffer Structure
The GHDLC unit and DSP always read and write to different areas in the RAM. Memory
is equally allocated to each of the receive and transmit buffer blocks (32 bytes each).
The DSP always writes to the block addresses. The switching between blocks is done
internally and does not concern the DSP.
4.7.7
Full Interrupt: A full interrupt is generated if:
• The receive buffer is full. The interrupt is issued immediately after the buffer has
• An end of a frame indication was detected at the beginning of a FSC frame. To avoid
Empty Interrupt: An empty interrupt is generated every time a transmit buffer was
emptied by the GHDLC.
Note: Messages with zero byte data content are not supported.
Preliminary Data Sheet
become full.
a loss of data in case of a buffer full indication followed by an end of frame indication,
this condition becomes only true if additionally there was no FULL interrupt during the
previous frame.
Transmit Buffer
Receive Buffer
GHDLC Interrupts
DSP write
DSP read
Block
Block
Block
Block
4-37
GHDLC receive
GHDLC transmit
Functional Description
PEB 20571
DELIC
2003-08