PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 205

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.11.5 REFCLK Control Register
REFCLK Control Register (CREFCLK) read/write
Reset value: 0003
Note: ’x’ = unused bits, read as 0.
REFCLK may be configured as an input or as an output. When configured as an input,
it may be used as a source for the on-chip DCXO 8kHz reference clock. This option is
handled by the DCXO Reference Clock Select Register (CREFSEL).
When configured as an output it is derived from XCLK input pin. In order to drive
REFCLK, XCLK may be divided by 256, 192, 4, 3 or 1.
REFCLKEN
REFDIV(2:0) REFCLK Pin Output Divider Selection
Preliminary Data Sheet
15
x
7
x
REFCLK Pin Output Enable
0 =
1 =
This determines the value by which the XCLK maximum clock of 2.048
MHz is divided internally.
000 =
001 =
010 =
011 =
100 =
H
14
6
x
x
REFCLK is input, the pad is not output enabled
REFCLK is output
Division by 256
Division by 192
Division by 4
Division by 3 (default)
Division by 1
13
x
5
x
12
4
x
x
6-65
REFCLKEN
11
x
3
10
x
2
Register Description
REFDIV(2:0)
Address: D084
9
x
1
DELIC
2003-08
8
0
x
H