PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 137

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

4.12.6
The IOM-2000 interface uses the same FSC like IOM-2, whereas the data clock
DCL2000 is a dedicated pin (always output).
4.12.7
REFCLK is an I/O pin for synchronizing the PCM interface (to 8 kHz or 512 kHz).
The clock master DELIC may synchronize the internal clocks to REFCLK by selecting
REFCLK as the reference clock source.
A clock slave DELIC may use REFCLK as output, when REFCLK is driven by the XCLK
input pin. The slave DELIC may transfer the XCLK signal to the clock master DELIC, and
enable the clock master to synchronize to a layer-1 device, which is connected to
another DELIC in the system.
4.12.8
Any of the next signals may be provided to the GHDLC channel as input clock:
1. LCLK Input Pin
2. 2.048 MHz, 4.096 MHz, or 8.192 MHz
Note that one of these signals must be selected as the clock of the GHDLC channel
when the DELIC is the clock master of this channel.
Preliminary Data Sheet
This option is possible only when a LNC interface is assigned to the GHDLC unit.
These clock signals are generated internally by the PCM clocking path. The selected
internal clock is also driven outward via LCLK.
IOM-2000 Clock Selection
REFCLK Configuration
GHDLC Clock Selection
4-53
Functional Description
PEB 20571
DELIC
2003-08