PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 130

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
must always get a ‘Write’ command for a write operation or a ‘Read’ for a read operation.
The Mailbox, however, reacts in the opposite way: it writes (puts data into a register)
upon receiving a ‘Read’ command and reads (drives data on the bus) upon receiving a
‘Write’ command.
4.10.4
The additional mode which is possible in work with some Siemens Ps is PEC mode. In
this case DMA controller is edge sensitive, so edges are provided on DREQ lines in order
to initiate every DMA transfer.
4.10.5
The Transmit Mailbox includes:
• 18-byte FIFO which is accessed by the OAK (for Read) as 9 “regular” addressed 16-
• 5-bit counter for the general number of transactions in current transfer (TX_CREG)
• 5-bit counter for the number of transactions that remains in the transfer (TX_CNT).
• 1-bit status register (TX_STAT).
The OAK is always the master of this transfer, i.e. the transfer is initiated b the OAK, but
the functions of control and arbitration during the transfer are done by the DMA.
For DMA request, the OAK requests transfer of data to the high-speed GHDLC channel.
It writes the number of bytes needed to the TX_CREG register which sets TX_BSY bit,
and causes the assertion of DREQT (“DMA Request Transmit”) pin.
For DMA acknowledge, the DMA grants the bus to OAK by driving DACK low, and
begins toggling the control lines. In Intel/Siemens (Mem-to-Mem) mode it drives the WR
line low when it writes to the Mailbox, and high when it reads from the memory on the
second side. RD line stays high during the complete transfer, because there are no
‘Read’ operations from here. DACK is low all the time. In Motorola (Mem-to-Mem) mode
it drives R/W line low for ‘Write’ operations when DACK and DS are low; when DMA
refers to the external memory, it drives DS high.
Note that in Fly-by mode the meaning of ‘Read’ and ‘Write’ commands is opposite for the
Mailbox. After every ‘Write’ operation the counter (TX_CNT) is decremented by one. If
the DMA stops the transaction before finishing, it has to drive DACK high. The OAK
continues driving DREQT high, stops decrementing TX_CNT and waits until DACK
becomes low.
After a write of TX_CREG bytes by the DMA to the Transmit Mailbox, the TX_CNT
becomes ‘0’. Then TX_BSY bit is reset to ’0’, and DREQT is deasserted. A reset of
TX_BSY bit may be programmed to generate an interrupt (INT1) to the OAK.
The OAK will then read TX_CREG bytes from the Mailbox to the GHDLC, the first byte
being the LSB of the least significant word of the FIFO. Note that in case of an odd
bit-wide registers and by the DMA (for Write) like a FIFO. One of the nine registers is
a “special” register like in the General Mailbox and has 3 addresses associated with it.
PEC Mode
Transmit Mailbox
4-46
Functional Description
DELIC
2003-08