PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 55

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

2.5
Table 2-19
Pin No.
DREQR
(11)
DSP_STOP
(63)
DCL (40):
TSC3 (83):
TSC2 (81)
DREQT
(10)
LTSC
(60)
Preliminary Data Sheet
Strap Pin Definitions
Strap Name Strap Function
CLOCK
MASTER
BOOT
TEST
(3:1)
EMULATION
BOOT
PLL
BYPASS
Strap Pins (Evaluated During Reset)
0:
(default)
1:
0:
(default)
1:
111 or
110:
(default)
101
100
011
010
001
0:
(default)
1:
0:
1:
(default)
Clock Slave
PDC and PFS are used as inputs.
PDC = 2.048 MHz
PFS = 4 kHz
Clock Master
PDC and PFS are used as outputs.
PDC = 2.048 MHz
PFS = 8 kHz
The DSP starts running from address FFFE
and executes the µP boot routine.
The DSP starts running directly from address
0000
Regular Work Mode
Test mode 1
Test mode 2
Test mode 3
Test mode 4
Test mode 5
After reset the boot-routine loads the program
RAM via the P-interface (via the general mail-
box).
After reset the boot-routine loads
the program RAM via the CDI mail-box (via the
JTAG interface).
DSP_CLK input pin (the DSP fall-back clock) is
used as source for the 61 MHz clock division
chain. (Only for testing).
The PLL output is used as the source for the
61 MHz clock division chain.
2-28
H
. The boot routine is not executed.
Pin Descriptions
PEB 20571
DELIC
2003-08
H
,