PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 94

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
RxSTA(1:0)
FECV
SLIP
FSYNC *
FCV *
MSYNC / LD *
Note: with * marked bits are not evaluated by the DELIC, only for VIP testing.
Bits SLIP, FECV and are directly available to the DSP software in the TRANSIU
receive data RAM.
Receiver Status Change (S/T, U
00 = Receiver is not synchronized to the line; no signal on line
01 = Level detected on line (any signal) (INF 1 in LT-S mode)
10 = Receiver is synchronized to the line, but not activated
11 = Receiver is synchronized and activated (INFO 4 for LT-T mode
INFO 3 for LT-S and U
Far-end Code Violation (S/T, U
0 = Normal operation
1 = Illegal code: FECV according to ANSI T1.605 detected (S/T)
Frame Slip Detected (LT-T)
0 = No frame slip detected
1 = A frame slip of more than 25 µs (tbd) was detected on the LT-T
F-Bit Synchronous (S/T + U
Code Violation in F-Bit detected (U
Multiframe Synchronous (U
channel
(INFO 2 in LT-T mode)
(INFO 0)
PN
4-10
)
PN
PN
), Level Detected (S/T), test mode!!
test mode only!!)
PN
PN
)
)
PN
test mode only!!)
Functional Description
DELIC
2003-08