PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 53

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 2-17
Pin
No.
Used for boundary scan according to IEEE 1149.1
54
53
52
51
Preliminary Data Sheet
Symbol
JTCK
TMS
TDI /
SCANEN
TDO
JTAG and Emulation Interface Pins (DELIC-PB)
In (I)
Out (O)
I
I
I
O
During
Reset
I
I
I
O
After
Reset
I
I
I
O
2-26
Function
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
Note: This pin must not be driven to low
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.
on the board during reset and
operation to ensure functioning of
DELIC
Pin Descriptions
PEB 20571
DELIC
2003-08