PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 164

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.2.3
ITSCR Register
Reset Value: 00
TS(15:0)
Table 6-14
ITSCR
Bit
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
Preliminary Data Sheet
DD0
DD0
DD0
DD0
DD0
DD0
not used
not used
not used
15
7
1 x 6 TS/frame
DD0
IOMU Tri-State Control Register
Every bit determines whether DD0/1 output is in tri-state during the time slot
sequence. The time slot sequence length, indices and port controlled by
each TS-bit is defined according the IOMU data rate mode (ICR.DR(1:0))
0 =
1 =
Tristate Control Assignment for IOM-2 Time Slots
H
0
1
2
3
4
5
14
6
DD0/1 is in tri-state during the related time slot sequence
DD0/1 is driven by the IOMU during the related time slot sequence
TS
DD0
DD0
DD0
DD0
DD0
DD0
DD0
DD0
DD0
1 x 12 TS/frame
13
5
DD0
0
1
2
3
4
5
6
7
8
12
4
read/write
TS
TS(15:8)
6-24
TS(7:0)
DD1
DD0
DD0
DD0
DD0
DD0
DD0
DD0
DD0
2 x 32 TS/frame
DD0/1
11
3
0-3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
0-3
10
2
TS
Address:
Set Address: D042
Reset Address: D043
Read Address: D044
Register Description
DD0
DD0
DD0
DD0
DD0
DD0
DD0
DD0
DD0
1 x 64 TS/frame
DD0/1
9
1
0-3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
32-35
DELIC
2003-08
TS
H
8
0
H
H