PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 14

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

List of Figures
Figure 1-1
Figure 1-2
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 2-1
Figure 2-2
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
Preliminary Data Sheet
Block Diagram of the DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Block Diagram of the DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
DELIC-LC in S/T and Upn Line Cards (up to 8 S/T and 16 Upn). . . . . 1-7
DELIC-LC in Uk0 Line Card for 16 Subscribers. . . . . . . . . . . . . . . . . . 1-8
DELIC-PB in Analog Line Card for 16 Subscribers . . . . . . . . . . . . . . . 1-8
DELIC-PB in Small PBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Pin Configuration DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pin Configuration DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Overview of IOM-2000 Interface Structure (Example with One VIP) . . 3-2
IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 3-4
IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 3-5
IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels) . . . . . . . . . . 3-6
IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels) . . 3-6
UPN State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
State Diagram of LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
LT-T Mode State Diagram (Conditional and Unconditional States) . . 3-20
IOM®-2 Interface in Digital Linecard Mode . . . . . . . . . . . . . . . . . . . . 3-23
DELIC in Multiplexed and in De-multiplexed Bus Mode . . . . . . . . . . 3-25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
S/Q Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
IOMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 4-18
IOM-2 Interface Open-Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
IOM-2 Interface Push-Pull Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
DRDY Signal Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DRDY Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
PCMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 4-25
HDLCU General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Data Processing in the GHDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
GHDLC Interface Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
GHDLC Receive and Transmit Buffer Structure . . . . . . . . . . . . . . . . 4-37
Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
DELIC Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Write Cycle in Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Read Cycle in Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Write Cycle in Intel/Infineon De-multiplexed Mode . . . . . . . . . . . . . . . 9-4
Read Cycle in Intel/Infineon De-multiplexed Mode . . . . . . . . . . . . . . . 9-5
Write Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . 9-6
Read Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . 9-7
Interrupt Acknowledge Cycle Timing in Motorola Mode. . . . . . . . . . . . 9-8
XIV
PEB 20571
DELIC
2003-08
Page