PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 222

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

In Motorola mode, an interrupt acknowledge cycle consists of one IACK pulse, during
which the interrupt vector is issued by the DELIC. In Intel/Infineon mode, an interrupt
acknowledge cycle consists of two IACK pulses. Note that the interrupt vector is issued
as a response to the second pulse. The source of the vector is the OAK Mailbox interupt
vector register (IVEC). The DSP determines the value stored in this register by a write
operation.
IREQ is not deactivated by the IACK pulses directly, but by a µP write access to OBUSY.
Table 9-7
Parameter
D-bus valid after IACK falling edge
D-bus float after IACK rising edge
IACK pulse width
Interval between two ACK pulses
1)
Figure 9-7
Figure 9-8
Preliminary Data Sheet
IACK
D
IACK
D
Valid only for Intel/Infineon mode.
Interrupt Acknowledge Cycle Timing
Interrupt Acknowledge Cycle Timing in Motorola Mode
Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode
t
WA
t
Symbol
t
t
t
t
HA
DADV
DADT
WA
HA
9-8
t
DADV
min.
0
0
25
10
Limit Values
t
vector
WA
1)
t
DADV
vector
max.
20
15
t
t
DADT
DADT
Unit
ns
ns
ns
ns
Timing Diagrams
Test
Condition
Output load
capacity of
50 pF
DELIC
2003-08