PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 124

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary Data Sheet
4.8.5
The internal data bus (GEXDBP) and program data bus (GIP) are tristate buses. Since
these buses must never float, the DCU keeps track of the bus activities. If during a
dedicated cycle no driver is on the bus, the DCU puts a default value on the bus.
4.8.6
The µP boot is the process which loads the external µP program RAM via the µP Mailbox
into the on-chip DSP program RAM. The boot is controlled by a boot routine residing in
the internal DSP program ROM. This routine is started upon DELIC reset according to
the BOOT strap pin status.
The second boot option is the emulation boot, which loads the monitor (BI routine) to the
program RAM. This routine enables the PC emulator to control the DSP.
At system start-up the program code for the DSP is transferred into the internal RAM
from the external uP. The contents for the program and data boot is delivered in a so
called HEX file.
The code format of the HEX file is the following:
Code,:,16 bit address, 16 bit opcode
C:0000 4180
C:0001 0018
C:0004 4180
C:0005 00BA
C:0006 4180
C:0007 00BD
C:000E 4180
C:000F 00BE ...
The program boot starts with the "Start Loading Program RAM" command which is
coming from the DELIC boot routine.
OCMD = 0x1F
This command must be polled from the uP because the interrupt is still not activated.
The uP confirms this with the "Start Boot" command.
MCMD = 0x55
The program code is now transferred in pieces of maximum 15 words by use of the
"Write Program Memory Command".
MDT0 = 0xDESTINATION_ADDRESS
MDTn = 0xOPCODE_WORDn
MCMD = 0xAn
Data Bus and Program Bus Arbitration
Boot Support
[n=1..15 number of code words to write to address++]
4-40
Functional Description
DELIC
2003-08