PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 42

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

2.4
Note: The column “During Reset” refers to the time period that starts with activation of
Table 2-10
Pin
No.
39
40
43
44
41
42
45
Preliminary Data Sheet
RESET input and ends with the deactivation of the RESIND output. During this
period, the DELIC’s strap pins (refer to Table 2-19) may be driven by external pull-
down or pull-up resistors to define DELIC’s configuration. If external pull-down or
pull-up resistors are not connected to the strap pins, the value of each strap pin
during reset will be determined by an internal pull-up or pull-down resistor,
according to the default strap value of each pin.
The user must ensure that connected circuits do not influence the sampling of the
strap pins during reset.
The column “After Reset” describes the behavior of every pin, from the
deactivation of the RESIND output until the DELIC’s registers are programmed.
Symbol
FSC
DCL
DD0
DD1
DU0
DU1
DRDY
Pin Definitions and Functions for DELIC-PB
IOM
In (I)
Out(O)
O
O
O(OD) High Z
O(OD) High Z
I
I
I
®
-2 Interface Pins (DELIC-PB)
During
Reset
O
TEST-
Strap (3),
(internal
pull-up),
refer to
Table 2-19
I
I
I
After
Reset
O
O
I
I
I
High Z Data Downstream IOM-2 Interface
High Z Data Downstream IOM-2 Interface
2-15
Function
Frame Synchronization Clock (8 kHz)
Used for both the IOM-2 and the IOM-
2000 interface
IOM-2 Data Clock 2.048 MHz or 4.096
MHz
Channel0
Channel1
Data Upstream IOM-2 Interface
Channel 0
Data Upstream IOM-2 Interface
Channel 1
D- Channel Ready
Stop/Go information for D-channel
control on S/T interface in LT-T.
Affects only IOM-2 port 0.
DRDY = 1 means GO
DRDY = 0 means STOP
Pin Descriptions
PEB 20571
DELIC
2003-08