PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 47

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 2-13
Pin
No.
6
5
29
89
Table 2-14
Pin
No.
87
88
76
78
Preliminary Data Sheet
Symbol In (I)
PFS
PDC
RxD0 /
LRxD2
TxD0 /
LTxD2
Symbol In (I)
IREQ
IACK
RESET
RESIND O
Microprocessor Bus Interface Pins (DELIC-PB) (Continued)
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB)
Out (O)
I/O
I/O
I
I
O
O(OD)
Out (O)
O
(OD)
I
I
During
Reset
I
I
I
High
Z
During
Reset
High Z
(OD)
I
I
O
After
Reset
I
I
I
High
Z
After
Reset
High Z
(OD)
I
I
O
2-20
Function
PCM Frame Synchronization Clock.
8 kHz/4 kHz when input or 8 kHz when
output.
Note: When PFS is configured as 4 kHz
PCM Data Clock (input or output)
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
PCM Receive Data Port 0
LNC Receive Serial Data Port 2
(HDLC and Async mode)
PCM Transmit Data Port 0
LNC Transmit Serial Data Port 2
(HDLC and Async mode)
Function
Interrupt Request is programmable to
push/pull (active high or low) or open-
drain. This signal is activated when the
DELIC requests a µP interrupt. When
operated in open drain mode, multiple
interrupt sources may be connected.
Interrupt Acknowledge
System Reset
DELIC is forced to go into reset state.
Reset Indication
Indicates that the DELIC is executing a
reset. The DELIC remains in reset
state for at least 500 µs after the
termination of the RESET pulse.
input,
restricted to 2.048 MHz input.
PDC
configuration
Pin Descriptions
PEB 20571
DELIC
2003-08
is