HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 11

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2.8 DTC Vector
Register (DTVECR)
7.3.2 Activation
Sources
7.3.8 Chain Transfer
Item
186
190
199
Page Revision (See Manual for Details)
Bit figure amended
Bit
Initial value
R/W
Notes 1 and 2 amended
Notes: 1. A value of 1 can only be written to the SWDTE bit.
2. DTVEC6 to DTVEC0 bits can only be written when SWDTE =
0.
Bit 7 DTC Software Activation Enable (SWDTE)
Description deleted
(Before) ... Enables or disables DTC activation by software. The
SWDTE bit is cleared by writing 0 after reading 1.
Enables or disables DTC activation by software.
Condition 2 added
[Clearing conditions]
1. When DISEL = 0 and ...
2. When 0 is written to the DISEL bit after a software-activated
data transfer end interrupt (SWDTEND) request has been sent to
the CPU.
Description added
...The activation source flag, in the case of RXI0, for example, is
the RDRF flag of SCI_0. As there are a number of activation
sources, the activation source flag is not cleared with the last
byte (or word) transfer. Take appropriate measures at each
interrupt.
Description added
... Figure 7.9 shows the memory map for chain transfer. When
activated, the DTC reads the register information start address
stored at the vector address, which corresponds to the activation
request, and then reads the first register information at that start
address. After the data transfer, the CHNE bit will be tested.
When it has been set to 1, DTC reads the next register
information located in a consecutive area and performs the data
transfer. These sequences are repeated until the CHNE bit is
cleared to 0.
:
:
:
SWDTE
R/(W) *
7
0
1
DTVEC6
R/(W) *
6
0
2
DTVEC5
R/(W) *
Rev.3.00 Mar. 26, 2007 Page xi of xlii
5
0
2
DTVEC4
R/(W) *
4
0
2
DTVEC3
R/(W) *
3
0
2
DTVEC2
R/(W) *
REJ09B0355-0300
2
0
2
DTVEC1
R/(W) *
(After)
1
0
2
DTVEC0
R/(W) *
0
0
2