HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 538

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Smart Card Interface
Interrupt Operation
There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI)
requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The
transmit end interrupt (TEI) request is not used in this mode.
When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.
When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
The relationship between the operating states and interrupt sources is shown in table 13.8.
Table 13.8 Smart Card Mode Operating States and Interrupt Sources
Operating State
Transmit Mode
Receive Mode
Data Transfer Operation by DTC
In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a
transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a
TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation
source, the DTC will be activated by the TXI request, and transfer of the transmit data will be
carried out. When DISEL in DTC is 0 and the transfer counter value is not 0, the TDRE and
TEND flags are automatically cleared to 0 when data transfer is performed. If DISEL is 1, or if
DISEL is 0 and the transfer counter value is 0, the DTC writes the transfer data to TDR but does
not clear the flags. Therefore, the flags should be cleared by the CPU. In the event of an error, the
SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time,
and the DTC is not activated. Thus, the number of bytes specified by the SCI and DTC are
transmitted automatically even in retransmission following an error
cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so
that an ERI request will be generated in the event of an error, and the ERS flag will be cleared.
Rev.3.00 Mar. 26, 2007 Page 496 of 772
REJ09B0355-0300
Normal
operation
Error
Normal
operation
Error
Flag
TEND
ERS
RDRF
PER, ORER
RIE
Enable Bit
TIE
RIE
RIE
Interrupt
Source
ERI
TXI
RXI
ERI
.
However, the ERS flag is not
DTC
Activation
Possible
Not possible
Possible
Not possible