HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 489

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Start transmission
Break output?
Initialization
TDRE = 1?
TEND = 1?
<End>
Yes
Yes
Yes
Yes
No
No
No
No
Section 12 Serial Communication Interface (SCI)
[1]
[2]
[3]
[4]
Note: * The case, in which the DTC
[1]
[2]
[3]
[4]
Rev.3.00 Mar. 26, 2007 Page 447 of 772
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC * is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
automatically clears the TDRE
flag, occurs only when DISEL in
DTC is 0 with the transfer
counter not being 0. Therefore,
the TDRE flag should be cleared
by CPU when DISEL is 1, or
when DISEL is 0 with the
transfer counter being 0.
REJ09B0355-0300