HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 370

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.4
Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 9.5 shows the register combinations used in buffer operation.
Table 9.5
Channel
0
When TGR is an output compare register: When a compare match occurs, the value in the
buffer register for the corresponding channel is transferred to the timer general register.
This operation is illustrated in figure 9.16.
When TGR is an input capture register: When input capture occurs, the value in TCNT is
transferred to TGR and the value previously held in the timer general register is transferred to the
buffer register.
This operation is illustrated in figure 9.17.
Rev.3.00 Mar. 26, 2007 Page 328 of 772
REJ09B0355-0300
Buffer register
Buffer Operation
Register Combinations in Buffer Operation
Timer General Register
TGR0A
TGR0B
Figure 9.16 Compare Match Buffer Operation
Compare match signal
Timer general
register
Comparator
Buffer Register
TGR0C
TGR0D
TCNT