HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 411

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by
which TCNT is cleared: by compare match A or B, or by an external reset input.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock ( ): /8, /64, and /8192.
The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Note:
Bit 4
CCLR1
0
1
Bit 2
CKS2
0
1
* If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
Bit 1
CKS1
0
1
0
1
TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
Bit 3
CCLR0
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
Clear is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
Description
Clock input disabled
Internal clock, counted at falling edge of /8
Internal clock, counted at falling edge of /64
Internal clock, counted at falling edge of /8192
For channel 0: count at TCNT1 overflow signal*
For channel 1: count at TCNT0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
Rev.3.00 Mar. 26, 2007 Page 369 of 772
Section 10 8-Bit Timers
REJ09B0355-0300
(Initial value)
(Initial value)