HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 95

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(8) Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Specified
by @aa:8
Effective Address Calculation
Figure 2.13 Branch Address Specification in Memory Indirect Mode
(a) Normal Mode
Branch address
Specified
by @aa:8
Rev.3.00 Mar. 26, 2007 Page 53 of 772
(b) Advanced Mode
Branch address
Reserved
REJ09B0355-0300
Section 2 CPU