HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 749

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
Notes: The method for writing to TCSR is different from that for general registers to prevent accidental overwriting.
For details see section 11.2.4, Notes on Register Access.
1. Can only be written with 0 for flag clearing.
2. When polling OVF with the interval timer interrupt disabled, read TSCR twice or more while OVF is set to 1.
:
:
:
R/(W)
Overflow Flag
OVF
0
1
7
0
*
1
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
Timer Mode Select
WT/IT
R/W
0
1
6
0
Interval timer mode: Sends the CPU an interval timer interrupt request
(WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal when
TCNT overflows
Timer Enable
TME
R/W
0
1
5
0
TCNT is initialized to H'00 and halted
TCNT counts
—
—
4
1
Note: *
CKS2 CKS1 CKS0
Clock Select
—
—
3
1
0
1
H'FFBC (W) H'FFBC (R)
The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
0
1
0
1
Rev.3.00 Mar. 26, 2007 Page 707 of 772
CKS2
R/W
2
0
0
1
0
1
0
1
0
1
/2 (initial value)
/64
/128
/512
/2048
/8192
/32768
/131072
CKS1
R/W
Clock
1
0
Appendix B Register Field
CKS0
*
R/W
2
0
0
REJ09B0355-0300
(when
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
Overflow period *
= 20 MHz)
WDT