HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 18
HD6412240
Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412240.pdf
(818 pages)
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12.2.8 Bit Rate Register
(BRR)
Table 12.3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
12.3.2 Operation in
Asynchronous Mode
Figure 12.4 Sample SCI
Initialization Flowchart
Figure 12.5 Sample
Serial Transmission
Flowchart
Figure 12.7 Sample
Serial Reception Data
Flowchart
Rev.3.00 Mar. 26, 2007 Page xviii of xlii
REJ09B0355-0300
Item
422
423
437
438
441
Page Revision (See Manual for Details)
Table 12.3 amended
Note * added to figure 12.4
Set TE and RE* bits in SCR to 1, and set RIE, TIE, TEIE, and
MPIE bits
Note: * Perform this set operation with the RxD pin in the 1
state. If the RE bit is set to 1 with the RxD pin in the 0 state, it
may be misinterpreted as a start bit.
Note * added to figure 12.5
[3] Serial transmission continuation procedure: ... Checking and
clearing of the TDRE flag is automatic when the DTC* is
activated by a transmit data empty interrupt (TXI) request, and ...
Note: * The case, in which the DTC automatically checks and
clears the TDRE flag, occurs only when DISEL in DTC is 0 with
the transfer counter not being 0. Therefore, the TDRE flag should
be cleared by CPU when DISEL is 1, or when DISEL is 0 with the
transfer counter being 0.
Note * added to figure 12.7
[5] Serial reception continuation procedure: ... The RDRE flag is
cleared automatically when the DTC* is activated by an RXI
interrupt and the RDR value is read.
Note: * The case, in which the DTC automatically clears the
RDRF flag, occurs only when DISEL in DTC is 0 with the transfer
counter not being 0. Therefore, the RDRF flag should be cleared
by CPU when DISEL is 1, or when DISEL is 0 with the transfer
counter being 0.
Bit Rate
(bit/s)
31250
38400
Bit Rate
(bit/s)
31250
38400
n
0
—
n
—
0
N
7
—
N
—
2
3.6864
(MHz)
8
Error
(%)
0.00
—
Error
(%)
—
0.00
(MHz)
n
0
—
N
3
—
4
Error
(%)
0.00
—
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