HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 185

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus release state
protocol, selection of the area partition unit and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access.
Bit 7
BRLE
0
1
Bit 6
BREQOE
0
1
Bit
Initial value
R/W
Bus Control Register L (BCRL)
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports.
External bus release is enabled.
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
:
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
(R/W)
—
4
1
Rev.3.00 Mar. 26, 2007 Page 143 of 772
(R/W)
—
3
1
ASS
R/W
2
1
Section 6 Bus Controller
(R/W)
REJ09B0355-0300
—
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0