HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 241

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3.8
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows the memory map for chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, which corresponds to the activation request,
and then reads the first register information at that start address. After the data transfer, the CHNE
bit will be tested. When it has been set to 1, DTC reads the next register information located in a
consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit
is cleared to 0.
DTC vector
address
Chain Transfer
Register information
start address
Figure 7.9 Chain Transfer Memory Map
Register information
Register information
CHNE = 1
CHNE = 0
Rev.3.00 Mar. 26, 2007 Page 199 of 772
Section 7 Data Transfer Controller
REJ09B0355-0300
Destination
Destination
Source
Source