HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 610

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HD6412240

Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 18 Power-Down Modes
18.8
Output of the clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the
corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle,
and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, clock output is disabled and input port mode is set.
Table 18.5 shows the state of the pin in each processing mode.
Table 18.5
Register Settings
DDR
0
1
1
Legend:
Rev.3.00 Mar. 26, 2007 Page 568 of 772
REJ09B0355-0300
: Don't care
Oscillator
RES
STBY
Clock Output Disabling Function
PSTOP
0
1
Pin State in Each Processing Mode
Figure 18.3 Hardware Standby Mode Timing (Example)
Normal Mode
High impedance High impedance High impedance High impedance
Fixed high
output
Sleep Mode
Fixed high
output
Software
Standby Mode
Fixed high
Fixed high
Oscillation
stabilization
time
t
OSC1
Hardware
Standby Mode
High impedance
High impedance
exception
handling
Reset

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