HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 770
HD6412240
Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412240.pdf
(818 pages)
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Appendix B Register Field
TSR2—Timer Status Register 2
Bit
Initial value
Read/Write
Rev.3.00 Mar. 26, 2007 Page 728 of 772
REJ09B0355-0300
Notes: 1. Can only be written with 0 for flag clearing.
2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.
:
:
:
Count Direction Flag
TCFD
0
1
R
7
1
TCNT counts down
TCNT counts up
—
—
6
1
R/(W)
Underflow Flag
TCFU
0
1
5
0
*
1
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
R/(W)
Overflow Flag
TCFV
0
1
4
0
*
1
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
—
—
3
0
—
—
2
0
R/(W)
TGRB Capture/Output Compare Flag
TGFB
H'FFF5
0
1
1
0
*
[Clearing conditions]
• When DTC *
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
1
TGRA Input Capture/Output Compare Flag
output compare register
capture signal while TGRB is functioning as input
capture register
bit of MRB in DTC is 0.
0
1
R/(W)
TGFA
0
0
[Clearing conditions]
• When DTC *
• When 0 is written to TGFA after reading
[Setting conditions]
• When TCNT = TGRA while TGRA is function-
• When TCNT value is transferred to TGRA by
*
DISEL bit of MRB in DTC is 0.
TGFA = 1
ing as output compare register
input capture signal while TGRA is functioning
as input capture register
1
2
is activated by TGIB interrupt while DISEL
2
is activated by TGIA interrupt while
TPU2
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