HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 320

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 I/O Ports
8.13.2
Table 8.23 shows the port G register configuration.
Table 8.23 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Notes: 1. Value of bits 4 to 0.
Port G Data Direction Register (PGDDR)
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read. PGDDR cannot be modified.
This register is a write-only register, and cannot be written by bit manipulation instruction. For
details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.
PGDDR is initialized by a power-on reset, and in hardware standby mode, to H'10 (bits 4 to 0) in
modes 1, 4, and 5, and to H'00 (bits 4 to 0) in modes 2, 3, 6, and 7. It retains its prior state after a
manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the
bus control output pins retain their output state or become high-impedance when a transition is
made to software standby mode.
Note: Modes 2, 3, 6, and 7 cannot be used in the H8S/2240.
Rev.3.00 Mar. 26, 2007 Page 278 of 772
REJ09B0355-0300
Bit
Modes 1, 4, 5
Initial value
R/W
Modes 2, 3, 6, 7
Initial value
R/W
2. Lower 16 bits of the address.
3. Initial value depends on the mode.
Register Configuration
:
:
:
:
:
Undefined
Undefined
—
—
—
7
Undefined
Undefined
—
—
—
6
Abbreviation
PGDDR
PGDR
PORTG
Undefined
Undefined
—
—
—
5
PG4DDR
W
W
4
1
0
R/W
W
R/W
R
PG3DDR
W
W
3
0
0
Initial Value*
H'00/H'10*
H'00
Undefined
PG2DDR
W
W
2
0
0
3
PG1DDR
1
W
W
1
0
0
Address*
H'FEBF
H'FF6F
H'FF5F
PG0DDR
W
W
0
0
0
2