HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 321

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Bit
Initial value
R/W
Modes 1, 2, 4, 5, and 6
Pins PG
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG
when the bit is cleared to 0.
Note: Modes 2 and 6 cannot be used in the H8S/2240.
Modes 3 and 7
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
Note: Modes 3 and 7 cannot be used in the H8S/2240.
0
4
is an output port when the corresponding PGDDR bit is set to 1, and an input port
to PG
:
:
:
Undefined
1
function as bus control output pins (CS0 to CS3) when the corresponding
—
—
7
Undefined
—
—
6
Undefined
—
—
5
PG4DR
R/W
4
0
Rev.3.00 Mar. 26, 2007 Page 279 of 772
PG3DR
R/W
3
0
PG2DR
R/W
2
0
PG1DR
Section 8 I/O Ports
REJ09B0355-0300
R/W
1
0
PG0DR
4
R/W
to PG
0
0
0
).