HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 192

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.3.6
The H8S/2245 Group can output chip select signals (CS0 to CS3) to areas 0 to 3, the signal being
driven low when the corresponding external space area is accessed. In normal mode, only the CS0
signal can be output.
Figure 6.3 shows an example of CSn (n = 0 to 3) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS3 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS3.
In ROM-enabled expansion mode, pins CS0 to CS3 are all placed in the input state after a power-
on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS3.
For details, see section 8, I/O Ports.
6.4
The CPU is driven by a system clock ( ), denoted by the symbol . The period from one rising
edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one,
two, or three states. Different methods are used to access on-chip memory, on-chip peripheral
modules, and the external address space.
Rev.3.00 Mar. 26, 2007 Page 150 of 772
REJ09B0355-0300
Chip Select Signals
Basic Timing
Address bus
CSn
Figure 6.3 CSn
CSn Signal Output Timing (n = 0 to 3)
CSn
CSn
T
1
Area n external address
Bus cycle
T
2
T
3