HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 335

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the
TCNT counter clearing source.
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Channel
0
Channel
1, 2
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
3. Bit 7 is reserved in channels 1and 2. It is always read as 0 and cannot be modified.
buffer register setting has priority, and compare match/input capture does not occur.
Bit 7
CCLR2
0
1
Bit 7
Reserved*
0
3
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture*
TCNT cleared by TGRD compare match/input
capture*
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Rev.3.00 Mar. 26, 2007 Page 293 of 772
Section 9 16-Bit Timer Pulse Unit (TPU)
2
2
1
REJ09B0355-0300
1
1
(Initial value)
(Initial value)