HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 15

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.2.5 Timer Status
Register (TSR)
9.7 Usage Notes
Figure 9.52 Contention
between Overflow and
Counter Clearing
Figure 9.53 Contention
between TCNT Write and
Overflow
10.2.2 Time Constant
Registers A0 and A1
(TCORA0, TCORA1)
Item
312
352
360
361
367
Page Revision (See Manual for Details)
Bit 0 Input Capture/Output Compare Flag A (TGFA)
Description amended
[Clearing conditions]
Description added
Note that the kinds of operation and contention described below
occur during TPU operation.
Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop
control register. The initial setting is for TPU operation to be
halted. Register access is enabled by clearing module stop
mode. For details, refer to section 18, Power-Down Modes.
Input Clock Restrictions
The input clock pulse width must be ...
Figure 9.52 amended
TGF flag
TCFV flag
Figure 9.53 amended
Address
Write signal
TCNT
TCFV flag
Description amended
... Note, however, that comparison is disabled during the T2 state
of a TCORA write cycle. ...
When DTC is activated by TGIA interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
When 0 is written to TGFA after reading TGFA = 1
Prohibited
H'FFFF
Rev.3.00 Mar. 26, 2007 Page xv of xlii
Prohibited
TCNT write cycle
TCNT address
T1
T2
REJ09B0355-0300
M
TCNT write data