HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 190

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.3.4
Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface should be referred to for further details.
Area 0
Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external
space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is switched between 128 kbytes and 2 Mbytes according to the state of the ASS
bit.
Areas 1 to 6
In external expansion mode, all of area 1 to 6 is external space.
When area 1 to 3 external space is accessed, the CS1 and CS3 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 and 6.
The size of areas 1 to 6 is switched between 128 kbytes and 2 Mbytes according to the state of the
ASS bit.
Area 7
Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space
excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is
enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME
bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external
space.
Only the basic bus interface can be used for the area 7.
The size of area 7 is switched between 15 Mbytes and 2 Mbytes according to the state of the ASS
bit.
Rev.3.00 Mar. 26, 2007 Page 148 of 772
REJ09B0355-0300