HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 163

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.4.3
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by means of the I and UI bits in the CPU's CCR, and ICR.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00
are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control
level 1 and other interrupts to control level 0), the situation is as follows:
Figure 5.6 shows the state transitions in these cases.
Figure 5.7 shows a flowchart of the interrupt acceptance operation in this case.
Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IRQ3 > IRQ0 ...)
When I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 interrupts are enabled
When I = 1 and UI = 1, only NMI interrupts are enabled
Exception handling execution
All interrupts enabled
Interrupt Control Mode 1
or I
Figure 5.6 Example of State Transitions in Interrupt Control Mode 1
1, UI
1
I
Only NMI interrupts enabled
0
I
I
1, UI
0
0
Rev.3.00 Mar. 26, 2007 Page 121 of 772
UI
0
Exception handling execution
Section 5 Interrupt Controller
IRQ3 interrupts enabled
Only NMI, IRQ2, and
or UI
REJ09B0355-0300
1