HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 314

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 I/O Ports
8.12.2
Table 8.21 shows the port F register configuration.
Table 8.21 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
This register is a write-only register, and cannot be written by bit manipulation instruction. For
details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,
4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
Rev.3.00 Mar. 26, 2007 Page 272 of 772
REJ09B0355-0300
Bit
Modes 1, 2, 4, 5, 6
Initial value
R/W
Modes 3 and 7
Initial value
R/W
Modes 1, 2, 4, 5, and 6
Pin PF
input port when the bit is cleared to 0.
2. Initial value depends on the mode.
Register Configuration
7
functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
:
:
:
:
:
PF7DDR
W
W
7
1
0
PF6DDR
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
PF5DDR
W
W
5
0
0
PF4DDR
W
W
4
0
0
R/W
W
R/W
R
PF3DDR
W
W
3
0
0
H'00
Initial Value
H'80/H'00*
Undefined
PF2DDR
W
W
2
0
0
2
PF1DDR
W
W
1
0
0
Address*
H'FEBE
H'FF6E
H'FF5E
PF0DDR
W
W
0
0
0
1